Recently, signal processing in applications of data communications or the like has been remarkably sped up. Accompanying this faster signal processing, faster conversion of an A/D (Analog to Digital) converter circuit is demanded. A highly accurate A/D conversion with a wide dynamic range is also demanded.
As one of measures for the demands as described above, a time-interleaved A/D converter device, in which two or more A/D converter circuits are disposed in parallel, is employed.
FIG. 8 is a diagram showing a typical configuration of the interleaved A/D converter device that uses the two A/D converter circuits. FIG. 9 is a timing diagram explaining an operation of a circuit in FIG. 8. A first A/D converter circuit 11 and a second A/D converter circuit 12 use clocks (CK1, CK2) with phases thereof shifted by 180 degrees as sampling clocks, respectively, and performs A/D conversion of an input signal. Frequencies (sampling frequencies) of the respective sampling clocks (CK1, CK2) are the same. A selector (also referred to as an “ADC output selector”) 10 performs switching between converted outputs (digital signals) of the first A/D converter circuit 11 and a second A/D converter circuit 12, thereby implementing the A/D converter device with a sampling frequency thereof twice as large as each of the sampling frequencies of the clock (CK1, or CK2).
FIG. 8 shows an example in which the first A/D converter circuit 11 and the second A/D converter circuit 12 are arranged in parallel. Assume that the number of A/D converter circuits used in parallel is set to M. When the A/D converter device of a predetermined sampling frequency is implemented, respective sampling frequencies of the A/D converter circuits arranged in parallel can be reduced to 1/M. That is, by arranging a plurality of low-speed A/D converter circuits in parallel, and driving the low-speed A/D converter circuits by multi-phase clocks, respectively, a high-speed A/D converter device can be implemented. Design of the A/D converter circuit itself therefore is facilitated.
However, this method has a problem that when a phase difference between the clocks for the A/D converter circuits used in parallel is not accurate, a spurious may occur in an A/D converted output, thereby deteriorating an SFDR (Spurious Free Dynamic Ratio) characteristic (refer to Non-patent Document 1).
A phase difference deviation between clocks, or a clock skew is generated due to buffering of a clock to be supplied from a clock generator to each A/D converter circuit, a wiring layout, a change in an environment such as temperature, and manufacturing variations. A method of reducing the clock skew that may cause serious characteristic deterioration therefore becomes necessary.
In order to improve an influence of the clock skew, there are proposed a plurality of approaches, in which A/D converter circuits are initially calibrated. Non-patent Document 1, for example, discloses a configuration in which a Ramp signal is used as a calibration signal, and the clock skew is corrected based on a result of conversion and an ideal conversion value.
Patent Document 1 discloses a configuration in which a clock is A/D converted, information on an advance or a delay in the clock is extracted from an MSB of a result of the conversion, and a variable delay is controlled, thereby adjusting the clock skew. This Patent Document 1 discloses a configuration of a time-interleaved A/D converter device in which a plurality of A/D converters are arranged in parallel, and operations of the respective A/D converters are time-interleaved. The time-interleaved A/D converter device includes first and second analog (digital) delay time synchronization loop circuits, and clock signals to be supplied to first and second A/D converters, respectively, are synthesized. A configuration in which delay control is performed by analog circuits (that perform D/A conversion) (in the analog delay time synchronization loop circuits) and a configuration in which the delay control is performed by digital circuits (each formed of a counter and a digital filter) (in the digital delay time synchronization loop circuits) are disclosed. Since the analog circuits and the digital circuits are different just in a manner in which a variable delay is controlled, a configuration of the digital circuits will be described below.
FIG. 10 is a diagram showing a configuration of the digital delay time synchronization loop circuits. Operation timings with respect to skew adjustment in the configuration in FIG. 10 are shown in FIGS. 11A, 11B, and 11C, respectively. FIG. 11A shows a case where a first variable delay circuit (18) is longer than a first delay circuit (20). FIG. 11B shows a case where the first variable delay circuit (18) is shorter than the first delay circuit (20). FIG. 11C shows an A/D conversion clock S110, a second A/D converter input S111, a first clock CK1 (S112), an MSB (Most Significant Bit) of an output (S113) of the first A/D converter circuit 14.
Referring FIG. 10, after an input switch (Switch) 13 has been switched to a B side and the A/D conversion clock S110 has been delayed by the first variable delay circuit (18), the A/D conversion clock S110 is input to a first A/D converter circuit 14 and a second A/D converter circuit 15. Then, using results of A/D conversion, the variable delay circuit 18 and a variable delay circuit 21 are adjusted, thereby adjusting a timing between the clock CK1 for the first A/D converter circuit 14 and a clock CK2 for the second A/D converter circuit 15. After timing adjustment (after there is no skew), the input switch 13 is switched to an A side. A first A/D converter input S100 is then input to the first and second conversion circuits 14 and 15 through the switch 13, and the time-interleaved A/D converter device operates as a usual A/D converter device.
Next, control over a variable delay will be described. The variable delay circuit 18 is controlled as follows.
The first A/D converter circuit 14 A/D converts the first A/D converter input S111 obtained by delaying the A/D conversion clock S110 by the variable delay circuit 18, using the clock CK1, and the MSB (S113) of a result of the conversion is counted by an UP/DOWN counter 37.
After results of the count by the UP/DOWN counter 37 are smoothed by a first digital filter (38), a smoothed value is input to the first variable delay circuit (18), thereby controlling a delay of the first variable delay circuit (18).
Until the second A/D converter input S11 and the clock CK1 are synchronized as shown in FIG. 11C, control over the first variable delay circuit (18) is repeated.
The UP/DOWN counter 37 performs an UP operation when the MSB (S113) of the output of the first A/D converter circuit 14 is one, and performs a DOWN operation when the MSB is zero.
When a digital value of the control signal decreases (when a count value of the UP/DOWN counter 37 decreases and an output digital value of the first digital filter (38) thereby decreases), a delay of the first variable delay circuit (18) decreases. When the digital value of the control signal increases (when the count value of the UP/DOWN counter 37 increases and the output digital value of the first digital filter (38) thereby increases), the delay of the first variable delay circuit (18) increases.
When a delay time of the first variable delay circuit (18) is longer than that of the delay circuit 20, as shown in FIG. 1A, the MSB (S113) of the output of the first A/D converter circuit 14 obtained using the clock CK1 becomes zero. When this result is accumulated and added by the UP/DOWN counter 37, the output of the UP/DOWN counter 37 gradually decreases.
For this reason, the delay time of the first variable delay circuit (18) decreases. Then, as shown in FIG. 11C, the second A/D converter input (S111) and the clock CK1 (S112) are finally synchronized.
On the other hand, as shown in FIG. 11B, when the delay time of the variable delay circuit 18 is shorter than that of the delay circuit 20, a reverse operation will be performed. That is, the MSB (S113) of the output of the first A/D converter circuit 14 obtained using the clock CK1 becomes one. When this result is accumulated and added by the UP/DOWN counter 37, the output of the UP/DOWN counter 37 gradually increases. For this reason, the delay time of the variable delay circuit 18 increases, and as shown in FIG. 11C, the second A/D converter input (S111) and the clock CK1 (S112) are finally synchronized.
The second variable delay circuit (21) is controlled by an UP/DOWN counter 40 that receives an output of the second A/D converter circuit 15 and a second digital filter (41) that averages outputs of the UP/DOWN counter 40. The second variable delay circuit (21) is controlled by a mechanism that is the same as for the first variable delay circuit (18).
Since a phase of the clock CK2 for the second A/D converter circuit 15 is different from a phase of the clock CK1 for the first A/D converter circuit 14 by 180 degrees, an UP/DOWN operation of the UP/DOWN counter 40 becomes reverse to that of the UP/DOWN counter 37.
Processing on the second variable delay circuit (21) is performed until the second A/D converter input (S111) and the clock CK2 (S115) are synchronized as shown in FIG. 11C.
After the control over the first variable delay circuit (18) has been completed, a phase relationship between the clock CK1 (S112) and the clock CK2 (S115) becomes a difference of 180 degrees.
[Non-Patent Document 1]
Huawen Jin, Lee, E. K. F. “A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] Volume 47, Issue 7, July 2000 Page(s): 603-613
[Non-Patent Document 2]
Miida Yosiro, “Numerical Calculation Method”, pp. 26-30, Morikita Publishing Co., Ltd., 1991
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-11-195988